A Low-Power Visual-Horizon Estimation Chip

Low Power Networks-on-Chip

Network on-Chip (NoC) is an interconnect fabric to connect sub-system blocks on a chip. The NoC should provide high bandwidth and low latency, should consume low energy, and should be compact. However, all these requirements are at odds and require tradeoffs at all levels. In this chapter, we discuss issues and challenges for future NoCs with demands for high bandwidth and low energy. Next, we ...

Towards Low-Power On-chip Auditory Processing

Machine perception is a difficult problem both from a practical or implementation point of view as well as from a theoretical or algorithmic point of view. Machine perception systems based on biological perception systems show great promise in many areas but they often have processing requirements and/or data flow requirements that are difficult to implement, especially in small or low-power sy...

Visual Receding Horizon Estimation for human presence detection

This paper deals with human presence detection by using a receding horizon estimator based on computer vision results. The visual position estimation problem is formulated into a nonlinear constrained optimization problem in the image plane. A global model combining the behavior of the human motion and the camera model is used to estimate the evolution of the visual features on a past finite ho...

Low - Power Low - Jitter On - Chip Clock Generation

A Novel Low Power Optimization for On-Chip Interconnection

This paper presents a low power design methodology for the Quasi Resonant Interconnection networks (QRN). This focuses mainly on reducing the power utilized at the receiver by replacing the existing delay element by a digitally controlled delay element. The analysis and design of the transmitter, receiver and the Interconnect and spiral inductor models are presented using 0.18μm CMOS technology...